1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to improvement of a pattern in which the power-supply and grounding lines connected to a peripheral circuit are arranged.
2. Description of the Related Art
The power-supply line and grounding line of a conventional semiconductor device are arranged in such a pattern as is shown in FIG. 1. In FIG. 1, reference numeral 1 denotes a semiconductor chip; 2 and 2' denote memory cell array regions; 3 denotes a peripheral circuit region; 4 denotes a power-supply line; 5 denotes a grounding line; 6 denotes a power-supply pad; and 7 denotes a grounding pad.
As is shown in FIG. 1, two memory cell array regions 2 and 2' are formed on the semiconductor chip 1. The peripheral circuit region 3 is formed between the two memory cell array regions 2 and 2'. A bonding pad region, an input protection circuit region, and other necessary circuit regions are formed in those regions around the memory cell array regions 2 and 2', except for the peripheral circuit region 3. (For simplicity, the bonding pad region, the input protection circuit region, and other necessary circuit regions will be collectively referred to as a "bonding pad region", unless otherwise indicated.)
The power-supply line 4 and the grounding line 5 are formed in the regions around the memory cell array regions 2 and 2', so as to supply a power-supply or ground potential to the peripheral circuit region 3 and the bonding pad region. In other words, the power-supply line 4 and the grounding line 5 are connected to both the peripheral circuit region 3 and the bonding pad region. The power-supply line 4 is also connected to the power-supply pad 6, while the grounding line 5 is also connected to the grounding pad 7.
In the pattern mentioned above, the power-supply line 4 and the grounding line 5 are arranged in the regions around the memory cell array regions 2 and 2'. Consequently, they occupy a certain area on the regions around the memory cell array regions 2 and 2'. In addition, they are required to have a certain width throughout the length, because a stable power-supply potential has to be applied even to their terminating points. If their widths are decreased, the impedance of the lines will increase, with the result that the potential necessary for a normal operation of the peripheral circuits will not be supplied. Moreover, the semiconductor memory device has to employ a larger chip in accordance with an increase of the capacity of the device. Therefore, the power-supply line 4 and the grounding line 5 arranged around the memory cell arrays 2 and 2' have been lengthened year by year. In accordance with this tendency, an increase in the resistance of the wiring lines has become a problem. In other words, the power-supply line 4 and the grounding line 5 arranged around the memory cell arrays 2 and 2' have to be widened in accordance with the increase in the capacity. Since, therefore, the power-supply line 4 and the grounding line 5 require a wide installation area, the size of the semiconductor chip is difficult to reduce.